Die, wafer and method of processing a wafer

ABSTRACT

A die in accordance with various embodiments may include a metallization area located proximate an edge of the die, and an electrical connection connected to the metallization area and running from the metallization area to the edge, wherein the electrical connection is free from metal. A wafer in accordance with various embodiments may include a die region having a metallization area, a kerf region having an electric or electronic device, and an electrical connection connecting the electric or electronic device with the metallization area, wherein the electrical connection is free from metal.

BACKGROUND

Various embodiments relate generally to a die, a wafer and a method ofprocessing a wafer.

Wafers may commonly be used in the fabrication of integrated circuits(ICs) or chips. A wafer may include a plurality of die regions orintegrally-formed dies. The die regions or dies may be separated by asingulation process such as sawing. Singulation of the dies may also bereferred to as dicing.

SUMMARY

A die in accordance with various embodiments may include: ametallization area located proximate an edge of the die; an electricalconnection connected to the metallization area and running from themetallization area to the edge, wherein the electrical connection isfree from metal.

A wafer in accordance with various embodiments may include: a die regionhaving a metallization area; a kerf region having an electric orelectronic device; an electrical connection connecting the electric orelectronic device with the metallization area, wherein the electricalconnection is free from metal.

A method of processing a wafer in accordance with various embodimentsmay include: providing a wafer having a die region and a kerf region;forming an electric or electronic device in the kerf region; forming ametallization area in the die region; forming an electrical connectionin or on the wafer connecting the electric or electronic device with themetallization area, the electrical connection being free from metal.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, like reference characters generally refer to the sameparts throughout the different views. The drawings are not necessarilyto scale, emphasis instead generally being placed upon illustrating theprinciples of various embodiments. In the following description, variousembodiments are described with reference to the following drawings, inwhich:

FIG. 1 shows a schematic plan view of a wafer for illustrating variousembodiments;

FIG. 2 shows an enlarged view of a section of a wafer;

FIG. 3 shows a schematic plan view of a section of a wafer in accordancewith an embodiment;

FIG. 4 shows a diagram illustrating a method of processing a wafer inaccordance with an embodiment;

FIG. 5A shows a schematic plan view of a die in accordance with anembodiment; and

FIG. 5B shows an enlarged view of section “B” in FIG. 5A.

DESCRIPTION

The following detailed description refers to the accompanying drawingsthat show, by way of illustration, specific details and embodiments inwhich the invention may be practiced. These embodiments are described insufficient detail to enable those skilled in the art to practice theinvention. Other embodiments may be utilized and structural, logical,and electrical changes may be made without departing from the scope ofthe invention. The various embodiments are not necessarily mutuallyexclusive, as some embodiments can be combined with one or more otherembodiments to form new embodiments. Various embodiments are describedin connection with devices, and various embodiments are described inconnection with methods, however it is to be understood that embodimentsdescribed in connection with devices may apply to the methods as well,and vice versa.

Wafers may commonly be used in the fabrication of integrated circuits(ICs) or chips. A wafer may include a plurality of die regions orintegrally-formed dies. The die regions or dies may be separated by asingulation process such as sawing. Singulation of the dies may also bereferred to as dicing.

Usually, dicing will be carried out along so-called dicing streets(sometimes also referred to as sawing streets or scribe lines) runningbetween the dies and may result in the removal of the wafer material anddestruction of any structures located in those dicing streets. Theregion of a wafer that will be affected (e.g. destroyed) by the dicingmay also be referred to as a kerf region of the wafer.

FIG. 1 shows a schematic plan view of a wafer 100 including a pluralityof die regions 101 separated by a kerf region 103 located between thedie regions 101. The number of die regions 101 may be arbitrary. Asshown in FIG. 1, the die regions 101 may have a quadratic shape, howeverthe die regions 101 may also have a rectangular shape, or any othershape in general. As shown in FIG. 1, the die regions 101 may bearranged in a rectangular array, however the die regions 101 may also bearranged differently. As shown in FIG. 1, the wafer 100 may have acircular shape, however the wafer 100 may also have a rectangular orquadratic shape, or any other shape in general.

In the fabrication of integrated circuits (ICs), process controlmonitoring (PCM) may be carried out. PCM may be associated withdesigning and fabricating special structures (also referred to as PCMtest structures) that can monitor technology specific parameters suchas, for example, Vth (threshold voltage) in CMOS (complementary metaloxide semiconductor) technologies or Vbe (base-emitter voltage) inbipolar technologies. These structures may be placed across the wafer atspecific locations along with the chip(s) produced so that a closer lookinto the process variation may be possible. PCM test structures usuallymay include one or more test devices (e.g. transistors) and associatedpads (also referred to as PCM pads) to electrically contact the testdevice(s). In many cases, the pads may contain or may be made of a metalor a metal alloy such as, for example, copper (Cu), aluminum (Al), or analloy containing Cu and/or Al (alternatively or in addition, othermetals or metal alloys).

Oftentimes, PCM test devices and pads may be placed in the kerf regionof a wafer, as is illustrated by FIG. 2.

FIG. 2 shows an enlarged view of a section of a wafer 200. The wafer 200may be similar to the wafer 100 shown in FIG. 1, and the section shownin FIG. 2 may, for example, correspond to section “A” of the wafer 100shown in FIG. 1. As illustrated in FIG. 2, one or more PCM test devices104 and pads 102 may be placed in a kerf region 103 of the wafer 200between adjacent die regions 101. The test devices 104 may be connectedto the pads 102 to electrically contact the test devices 104.

Placing the PCM test structures in the kerf region of a wafer may havethe effect that the test devices may be destroyed in a later dicingprocess. Thus, it may, for example, be possible to prevent that fullyfunctional single devices will be delivered to the end customer, whichmight enable competitors to characterize the single devices. However,when dicing the wafer (for example, by means of sawing), cracks mayoccur at structures having large metal areas such as the PCM pads 102shown in FIG. 2. Such cracks may result in chip failure out in the fieldon the customer's side. Thus, it may be desirable to provide anarchitecture that may avoid metal-induced crack formation during diesingulation.

FIG. 3 shows, as a schematic plan view, a section of a wafer 300 inaccordance with an embodiment. The wafer 300 may, for example, be asemiconductor wafer such as, for example, a silicon wafer (alternativelyor in addition, any other suitable semiconductor material or materials,including compound semiconductor materials, may be used as well) inaccordance with some embodiments.

In accordance with various embodiments, the wafer 300 may include a dieregion 301. In accordance with various embodiments, the die region 301may correspond to the area of a die, which may be obtained from thewafer 300 by a die singulation or dicing process.

In accordance with some embodiments, the wafer 300 may include at leastone additional die region 301 a, as shown. In accordance with someembodiments, the at least one additional die region 301 a may correspondto the area of at least one additional die that may be obtained from thewafer 300 by the die singulation or dicing process. In accordance withsome embodiments, the at least one additional die region 301 a may beconfigured in the same or a similar manner as the die region 301.

Clearly, in accordance with some embodiments, the wafer 300 may includea plurality of die regions (e.g. die regions 301, 301 a and possiblyadditional die regions (not shown)) or integrally-formed dies. Thus, thewafer 300 may, for example, have a similar structure as the wafer 100shown in FIG. 1 (for example, die regions 301, 301 a may correspond totwo neighboring die regions 101 of wafer 100 in FIG. 1), and the wafer300 may later be diced (e.g. by sawing) to obtain single dies.

In accordance with various embodiments, the die region 301 may have ametallization area 302, as shown. In other words, a metallization area302 may be located in the die region 301. In accordance with someembodiments, the metallization area 302 may, for example, be located ina peripheral region of the die region 301, for example proximate an edgeof the die region 301. In accordance with some embodiments, themetallization area 302 may include or may be a pad. In accordance withsome embodiments, the pad may contain or may be made of a metal or ametal alloy such as, for example, copper (Cu), aluminum (Al), or analloy containing Cu and/or Al. Alternatively or in addition, the pad maycontain or may be made of other metals or metal alloys.

In accordance with some embodiments, the metallization area 302 may bedisposed on or above an upper surface of the wafer 300 in the die region301.

In accordance with some embodiments, the die region 301 may have atleast one additional metallization area 302 a, 302 b (a first additionalmetallization area 302 a and a second additional metallization area 302b are shown as an example, however there may be only one additionalmetallization area or more than two additional metallization areaspresent in accordance with some embodiments). The additionalmetallization area(s) may be configured in the same or a similar manneras the metallization area 302, for example as pads.

In accordance with various embodiments, the wafer 300 may include a kerfregion 303. The kerf region 303 may be located adjacent the die region301.

The term “kerf region” as used herein may be understood to refer to aregion of a wafer that may be at least partially removed or destroyed ina die singulation or dicing process. For example, in accordance withvarious embodiments, the kerf region 303 shown in FIG. 3 mayillustratively include or correspond to one or more dicing streets orscribe lines 306 of the wafer 300 (in other words, a line or lines alongwhich the wafer 300 may be diced (e.g. cut, e.g. by means of sawing)).In accordance with some embodiments, the kerf region 303 may be locatedat least partially between the die region 301 and at least oneadditional die region (e.g. the additional die region 301 a, as shown inFIG. 3, and possibly other additional die regions (not shown)) of thewafer 300. For example, in accordance with some embodiments, the wafer300 may include a plurality of die regions 301, 301 a that may beseparated by the kerf region 303 that may be formed between the dieregions 301, 301 a, e.g. similar to the wafer 100 shown in FIG. 1. Thenumber of die regions of the wafer 300 may be arbitrary in accordancewith various embodiments.

The die region 301 or the plurality of die regions of the wafer 300 mayhave any shape, for example a quadratic or rectangular shape inaccordance with some embodiments, however any other shape may bepossible as well in accordance with some embodiments.

In accordance with some embodiments, the die regions may be arranged ina rectangular array, e.g. similar to the array shown in FIG. 1. However,in accordance with other embodiments, the die regions may be arrangeddifferently.

In accordance with various embodiments, the kerf region 303 may have atleast one electric or electronic device 304 such as, for example, aresistor, and/or a capacitor, and/or a transistor, and/or other electricor electronic devices. In other words, one or more electric orelectronic devices 304 may be located in the kerf region 303, as shown.In accordance with various embodiments, the dimensions of the device 304(e.g. the width of the device) may be configured such that the device304 may be fully accommodated in the kerf region 303.

In accordance with some embodiments, the at least one electric orelectronic device 304 may include or may be a test device, for example aPCM (process control monitor) test device in accordance with someembodiments.

The term “test device” as used herein may be understood to refer to anelectric or electronic component that may be used solely for testing inconnection with a fabrication process, in contrast to e.g. other“operational devices” that might be used for testing as well, but mayalso be necessary or desirable for operation of a finished device. Thedistinction, therefore, may be seen in that a “test device” may besacrificed or discarded after or at some point during fabrication. Thetest device or devices located in the kerf region 303, for example, maybe destroyed during a die singulation or dicing process in accordancewith various embodiments.

In accordance with various embodiments, the wafer 300 may include anelectrical connection or connection region 305 connecting the electricor electronic device 304 with the metallization area 302, as shown.

In accordance with some embodiments, the electrical connection 305 maybe disposed in the wafer, or on or above the upper surface of the wafer300.

In accordance with various embodiments, the electrical connection 305may be arranged such that a first part 305′ of the electrical connection305 may be located in the kerf region 303, and a second part 305″ of theelectrical connection 305 may be located in the die region 301, asshown. Illustratively, the electrical connection 305 may run from thedevice 304 located in the kerf region 303 to the metallization area 302(e.g. metal pad) located in the die region 301, and a part of theelectrical connection 305 may thus cross a boundary 307 between the kerfregion 303 and the die region 301, as shown.

In accordance with some embodiments, the electrical connection 305 maybe free from metal. The term “free from metal”, as used herein, mayrefer to electrically conductive materials other than a metal or metalalloy, and may include, for example, polysilicon, electricallyconductive carbon, a doped semiconductor material (e.g. doped silicon),a silicide, a polycide, or other suitable electrically conductivematerials that are not metals or metal alloys.

For example, in accordance with some embodiments, the electricalconnection 305 may include or may be made of polysilicon. For example,in accordance with some embodiments, the electrical connection 305 mayinclude or may be an electrically conductive trace made of polysilicon,which may be be formed in the wafer, or on or above the upper surface ofthe wafer 300.

In accordance with some embodiments, the electrical connection 305 mayinclude or may be made of doped semiconductor material (e.g. dopedsilicon). For example, in accordance with some embodiments, theelectrical connection 305 may include or may be a doped region formed inthe wafer, for example a doped region located near the upper surface ofthe wafer. In accordance with some embodiments, the doped region may,for example, be a well region (e.g. a diffused well region) in thewafer.

In accordance with some embodiments, the wafer may include one or moreadditional electrical connections or connection regions connecting theelectric or electronic device 304 with one or more additionalmetallization areas of the die region 301 and/or with one or moremetallization areas of one or more additional die regions. In accordancewith some embodiments, the additional electrical connection(s) may beconfigured in the same or a similar manner as the electrical connection305. As an example, two additional electrical connections or connectionregions 305 a, 305 b are shown in FIG. 3, connecting the device 304 withthe additional metallization areas 302 a, 302 b. As shown in FIG. 3, afirst additional electrical connection 305 a may connect the device 304with the first additional metallization area 302 a (e.g. pad), and asecond additional electrical connection 305 b may connect the device 304with the second additional metallization area 302 b (e.g. pad) inaccordance with some embodiments.

In accordance with some embodiments, the die region 301 may include oneor more electric and/or electronic devices, or one or more integratedcircuits (ICs) including one or more electric and/or electronic devices.The electric and/or electronic devices, or the integrated circuit(s),may, for example, be formed in an active region of the die region 301 inaccordance with some embodiments.

In accordance with various embodiments, the metallization area 302located in the die region 301 may be a pad associated with the electricor electronic device 304 (e.g. test device) located in the kerf region303, for example a pad associated with a PCM test device in accordancewith some embodiments.

In accordance with some embodiments, the one or more additionalmetallization areas (e.g. pads) 302 a, 302 b may also be associated orconnected with the electric or electronic device 304 (e.g. test device)located in the kerf region 303.

In accordance with some embodiments, the electric or electronic device304 (e.g. test device, e.g. PCM test device) located in the kerf region303 may be connected with a plurality of metallization areas (e.g. pads,e.g. PCM pads), wherein at least one of the plurality of metallizationareas may be located in one of the plurality of die regions (e.g. in thedie region 301 shown in FIG. 3) and at least one other of the pluralityof metallization areas may be located in another one of the plurality ofdie regions (e.g. in the additional die region 301 a shown in FIG. 3).In other words, a plurality of metallization areas associated with theelectric or electronic device 304 may be distributed over at least twoof a plurality of die regions in accordance with some embodiments (notshown).

In accordance with some embodiments, the die region 301 may include oneor more additional metallization areas (not shown), e.g. pads, that maybe associated or connected with electric and/or electronic deviceslocated in the die region 301.

As shown in FIG. 3, all the metallization areas 302, 302 a, 302 b may belocated outside the kerf region 303 and may be connected to the device304 located inside the kerf region 303 via the electrical connections305, 305 a, 305 b. The electrical connections 305, 305 a, 305 b may bemade of an electrically conductive material other than a metal or metalalloy, for example of polysilion in accordance with some embodiments.Thus, the kerf region 303 may be free from large metallization areas inaccordance with various embodiments. In particular, edge regions (e.g.the boundary 307 between the kerf region 303 and the die region 301 anda boundary 307 a between the kerf region 301 and the additional dieregion 301 a, and possibly boundaries between the die region 301 andother additional die regions (not shown)) of the kerf region 303 ordicing street 306 may be free from metal in accordance with someembodiments.

In accordance with some embodiments, the electrical connection 305 maybe connected to an electrical contact 308 (e.g. Met1 contact) of thedevice 304, as shown. Similarly, one or more of the additionalelectrical connections 305 a, 305 b (if present) may be connected to oneor more additional electrical contacts 308 a, 308 b (e.g. Met1 contacts)of the device 304 in accordance with some embodiments.

In accordance with some embodiments, a width 309 of the kerf region 303,corresponding for example to a width of a dicing street 306 and/orcorresponding to a distance between the die region 301 and an adjacentdie region, e.g. the additional die region 301 a as shown in FIG. 3,may, for example, be in the micrometer range, for example on the orderof a few tens of a micrometer, e.g. about 50 μm in accordance with oneembodiment, although it will be understood that, in general, the width309 may e.g. depend on the process technology used so that other valuesof the width 309 may be possible as well in accordance with otherembodiments.

In accordance with some embodiments, a distance 310 between themetallization area 305 (e.g. pad) and the kerf region 303 (similarly,distances between additional metallization areas 305 a, 305 b and thekerf region 303) may, for example, be in the micrometer range, forexample on the order of a few tens of a micrometer, for example in therange from about 10 μm to about 50 μm in accordance with someembodiments, e.g. about 30 μm in accordance with one embodiment,although it will be understood that, in general, the distance 310 maye.g. depend on the process technology and other values of the distance310 may be possible as well in accordance with other embodiments.

In accordance with some embodiments, a lateral dimension (e.g. lengthand/or width, or diameter) 311 of the metallization area 302 (similarlylateral dimensions of one or more of the additional metallization areas302 a, 302 b) may, for example, be in the micrometer range, for exampleon the order of a few tens of a micrometer, e.g. about 50 μm inaccordance with one embodiment, although it will be understood that, ingeneral, the dimension 311 may e.g. depend on the process technologyused and other values of the dimension 311 may be possible as well inaccordance with other embodiments.

FIG. 4 shows a diagram illustrating a method 400 of processing a waferin accordance with an embodiment.

In 402, a wafer may be provided. The wafer may have a die region and akerf region. In accordance with some embodiments, the kerf region may belocated adjacent the die region. In accordance with some embodiments,the wafer may have a plurality of die regions and the kerf region may belocated at least partially between at least two of the plurality of dieregions. The wafer, the die region or die regions, and/or the kerfregion may further be configured in accordance with one or moreembodiments described herein.

In 404, at least one electric or electronic device may be formed in thekerf region. In accordance with some embodiments, the at least oneelectric or electronic device may include or may be a test device, forexample a PCM test device in accordance with some embodiments. Inaccordance with some embodiments, a plurality of electric or electronicdevices may be formed in the kerf region. In accordance with someembodiments, at least one of the plurality of electric or electronicdevices may include or may be a test device, e.g a PCM test device inaccordance with some embodiments. The electric or electronic device ordevices may further be configured in accordance with one or moreembodiments desribed herein.

In 406, at least one metallization area may be formed in the die region.In accordance with some embodiments, the metallization area may be apad, for example a PCM pad in accordance with some embodiments. The padmay contain or may be made of a metal or a metal alloy such as, forexample, copper (Cu) or aluminum (Al), or an alloy containing Cu and/orAl. Alternatively or in addition, the pad may contain or may be made ofother metals or metal alloys. In accordance with some embodiments, themetallization area (e.g. pad) may be formed in a peripheral region ofthe die region, for example, proximate (in other words, close to) aboundary between the kerf region and the die region. In accordance withsome embodiments, a plurality of metallization areas, e.g. a pluralityof pads, may be formed in the die region. The metallization area orareas may further be configured in accordance with one or moreembodiments described herein.

In 408, an electrical connection may be formed in or on the wafer. Theelectrical connection may connect the electric or electronic device withthe metallization area. The electrical connection may be free frommetal. In other words, the electrical connection may be made of anelectrically conductive material or materials other than a metal ormetal alloy. For example, in accordance with some embodiments, theelectrical connection may contain or may be made of polysilicon,electrically conductive carbon, a silicide, or a polycide.Alternatively, the electrical connection may contain or may be made ofother electrically conductive materials. For example, in accordance withsome embodiments, the electrical connection may be a doped semiconductorregion in the wafer, e.g. a well region (e.g. diffused well region) inaccordance with some embodiments. In accordance with some embodiments, aplurality of electrical connections may be formed in or on the wafer.The plurality of electrical connections may connect the electric orelectronic device in the kerf region with a plurality of metallizationareas (e.g. pads) in the die region. The electrical connection orconnections may further be configured in accordance with one or moreembodiments described herein.

In accordance with some embodiments, the at least one electric orelectronic device may include or may be a PCM test device and themetallization area or areas may include or may be a PCM pad or pads, andat least one PCM test may be carried out after forming the electricalconnection or connections using the PCM test device and PCM pad or pads,as shown in 410.

In accordance with some embodiments, the wafer may be diced (forexample, by means of sawing) along the kerf region after forming theelectrical connection or connections, as shown in 412. In accordancewith some embodiments, the dicing may be carried out after a PCM testhas been carried out. During the dicing, the kerf region of the wafermay be removed thereby obtaining one or more singulated dies. Inaccordance with various embodiments, the dicing may lead to thedestruction of the electric or electronic device(s), e.g. the PCM testdevice(s), located in the kerf region. In accordance with variousembodiments, crack formation at metallization areas may be substantiallyreduced or avoided as, for example, metallization areas (e.g. pads)associated with the electric or electronic device(se), e.g. the PCM testdevice(s) in the kerf region, may be located in the die region(s) andthus outside the kerf region. Thus, the kerf region, or at least edgesof the kerf region, may be substantially or completely free from metalor metal alloys.

FIG. 5A and FIG. 5B are schematic views for illustration of a die inaccordance with an embodiment.

FIG. 5A shows a schematic plan view of a die 500 in accordance with anembodiment, and FIG. 5B shows an enlarged view of section “B” of the die500 shown in FIG. 5A.

Illustratively, the die 500 may be obtained by dicing the wafer 300shown in FIG. 3 along the kerf region 303 (for example, using a saw),thereby removing the material of the kerf region 303 (including thedevice(s) 304 and those parts of the electrical connections 305, 305 a,305 b located in the kerf region 303). In other words, the area of die500 may illustratively correspond to the die region 301 of wafer 300shown in FIG. 3, and the same reference numerals denote the sameelements as in FIG. 3.

The die 500 may include metallization areas 302, 302 a, 302 b locatedproximate an edge 507 of the die 500. Three metallization areas 302, 302a, 302 b are shown as an example and corresponding to the embodimentshown in FIG. 3. However, in accordance with other embodiments, the die500 may include only one or only two metallization areas, or may includemore than three metallization areas. The edge 507 of the die 500 maycorrespond to the boundary 307 between the kerf region 303 and the dieregion 301 of wafer 300 in FIG. 3. In accordance with some embodiments,the metallization areas 302, 302 a, 302 b may be located in a peripheralregion 510 of the die 500, as shown. In accordance with someembodiments, the die 500 may include one or more electric and/orelectronic devices, e.g. one or more integrated circuit elements, suchas resistors, capacitors, transistors, diodes, thyristors, etc., (notshown), that may, for example be located in an active region 520 of thedie 500.

The die 500 may include electrical connection 305 connected tometallization area 302 and running from metallization area 302 to theedge 507. As described above, the electrical connection 302 may be freefrom metal. Similarly, in accordance with some embodiments, the die 500may include additional electrical connections 305 a, 305 b connected toadditional metallization areas 302 a, 302 b, as shown.

Illustratively, the die 500 may include one or more metallization areas302, 302 a, 302 b (e.g. one or more pads, e.g. PCM pads) that may belocated in a peripheral region 510 of the die 500 proximate the edge507, and an electrical connection 305, 305 a, 305 b (e.g. anelectrically conductive trace formed in the die 500, or on or above theupper surface of the die 500 and e.g. containing or being made ofpolysilicon, alternatively another electrically conductive materialother than a metal or metal alloys; or a doped region (e.g. a wellregion, e.g. a diffused well region) in the die 500, e.g. near the uppersurface of the die 500) may in each case lead from the respectivemetallization area 302, 302 a, 302 b towards the edge 507 of the die 500and may terminate at or close to the edge 507 of the die 500, as shown.

Clearly, the edge 507 may have been obtained by dicing (e.g. sawing) thewafer 300 along the kerf region 303 or dicing street 306. Thus, inaccordance with various embodiments, the one or more electricalconnections 305, 305 a, 305 b may terminate at or close to a sawing edgeof the die 500.

In accordance with some embodiments, the die 500 may include one or moreadditional metallization areas 530 (e.g. pads) that may, for example, belocated in the peripheral region 510 of the die 500, as shown. Inaccordance with some embodiments, the metallization area(s) 530 (e.g.pad(s)) may serve to electrically contact the one or more electricand/or electronic devices of the die 500 located in the active region520 of the die 500. Clearly, the metallization areas 302, 302 a, 302 b(e.g. pads) may differ from the additional metallization area(s) 530 inthat the metallization areas 302, 302 a, 302 b may have been formedand/or configured to electrically contact electric or electronic devices(e.g. PCM test devices) located in a kerf region of a wafer (e.g. kerfregion 303 of wafer 300), which may be no longer present after dicingthe wafer, whereas the additional metallization areas (e.g. pads) 530may have been formed or configured to electrically contact one or moreelectric or electronic devices of the die 500 (for example, operationaldevices of the die 500 that may be used for operation of the die 500)located, for example, in the active region 520 of the die 500. Thus, inaccordance with various embodiments, the additional metallization areas(e.g. pads) 530 may be connected to one or more electric or electronicdevices of the die 500 while the metallization areas 302, 302 a, 302 bmay be not connected to any of the electric or electronic devices of thedie 500. For example, the electrical connection 305 may be the onlyelectrical connection connected to the metallization area 302 inaccordance with some embodiments. Similarly, the electrical connection305 a may be the only electrical connection connected to themetallization area 302 a and the electrical connection 305 b may be theonly electrical connection connected to the metallization area 302 b inaccordance with some embodiments.

A die in accordance with various embodiments may include a metallizationarea located proximate an edge of the die; and an electrical connectionconnected to the metallization area and running from the metallizationarea to the edge, wherein the electrical connection is free from metal.

In accordance with various embodiments, the electrical connection mayterminate at or close to the edge.

In accordance with some embodiments, the electrical connection mayinclude an electrically conductive trace formed in the die, or on orabove an upper surface of the die.

In accordance with some embodiments, the electrical connection maycontain or may be made of polysilicon.

In accordance with some embodiments, the electrical connection maycontain or may be made of carbon.

In accordance with some embodiments, the electrical connection maycontain or may be made of a silicide.

In accordance with some embodiments, the electrical connection maycontain or may be made of a polycide.

In accordance with some embodiments, the electrical connection mayinclude or may be a doped region formed in the die, for example near anupper surface of the die.

In accordance with some embodiments, the doped region may be a wellregion, e.g. a diffused well region, in the die.

In accordance with some embodiments, the metallization area may includeor may be a pad, for example a process control monitor (PCM) pad inaccordance with an embodiment. The pad may contain or may be made of ametal or a metal alloy such as, for exampel, copper (Cu) or aluminum(Al), or an alloy containing Cu and/or Al. Alternatively or in addition,the pad may contain or may be made of other metals or metal alloys.

A wafer in accordance with various embodiments may include: a die regionhaving a metallization area; a kerf region having an electric orelectronic device; and an electrical connection connecting the electricor electronic device with the metallization area, wherein the electricalconnection is free from metal.

In accordance with various embodiments, the kerf region may correspondto a region of the wafer to be removed in a dicing process.

In accordance with some embodiments, the kerf region may be locatedadjacent to the die region.

In accordance with some embodiments, the metallization area may belocated in a peripheral region of the die region.

In accordance with some embodiments, the metallization area may belocated proximate a boundary between the kerf region and the die region.

In accordance with some embodiments, the electrical connection mayinclude or may be an electrically conductive trace formed in the wafer,or on or above an upper surface of the wafer.

In accordance with some embodiments, the electrical connection maycontain or may be made of polysilicon.

In accordance with some embodiments, the electrical connection maycontain or may be made of carbon.

In accordance with some embodiments, the electrical connection maycontain or may be made of a silicide.

In accordance with some embodiments, the electrical connection maycontain or may be made of a polycide.

In accordance with some embodiments, the electrical connection mayinclude or may be a doped region formed in the wafer, for examplelocated near an upper surface of the wafer.

In accordance with some embodiments, the doped region may be a wellregion, e.g. a diffused well region, in the wafer.

In accordance with some embodiments, the metallization area may includeor may be a pad, e.g. a process control monitor (PCM) pad. The pad may,for example, contain or be made of a metal or a metal alloy such as, forexample, copper (Cu) or aluminum (Al), or an alloy containing Cu and/orAl. Alternatively or in addition, the pad may contain or may be made ofother metals or metal alloys.

In accordance with some embodiments, the electric or electronic devicemay include or may be a test device.

In accordance with some embodiments, the test device may be a processcontrol monitor (PCM) test device.

In accordance with some embodiments, the wafer may include at least oneadditional die region, and the kerf region may be located at leastpartially between the die region and the at least one additional dieregion.

In accordance with some embodiments, the wafer may include a pluralityof die regions, and the kerf region may be located between the pluralityof die regions.

A wafer in accordance with various embodiments may include: a die regionhaving a pad; a kerf region having a test device; an electricalconnection connecting the test device in the kerf region with the pad inthe die region, the electrical connection being made of an electricallyconductive material other than a metal or metal alloy.

In accordance with some embodiments, the test device may include or maybe a process control monitor (PCM) test device.

In accordance with some embodiments, the electrical connection maycontain or may be made of polysilicon.

In accordance with some embodiments, the electrical connection maycontain or may be made of carbon.

In accordance with some embodiments, the electrical connection maycontain or may be made of a silicide.

In accordance with some embodiments, the electrical connection maycontain or may be made of a polycide.

In accordance with some embodiments, the pad may contain or may be madeof a metal or a metal alloy such as, for example, copper (Cu) oraluminum (Al), or an alloy containing Cu and/or Al. Alternatively or inaddition, the pad may contain other metals or metal alloys.

A wafer in accordance with various embodiments may include: a pluralityof integrally-formed dies separated from each other by a kerf regionformed between them, at least one of the plurality of dies having atleast one process control monitor (PCM) pad containing metal or a metalalloy; at least one PCM test device located in the kerf region andelectrically connected to the at least one PCM pad via at least oneelectrical connection that is free from metal.

In accordance with some embodiments, the at least one electricalconnection may include or may be an electrically conductive tracecontaining or being made of polysilicon and formed in the wafer or on orabove an upper surface of the wafer.

In accordance with some embodiments, the at least one electricalconnection may include or may be a doped region, e.g. a well region,e.g. a diffused well region, formed in the wafer.

A method of processing a wafer in accordance with various embodimentsmay include: providing a wafer having a die region and a kerf region;forming an electric or electronic device in the kerf region; forming ametallization area in the die region; forming an electrical connectionin or on the wafer connecting the electric or electronic device with themetallization area, the electrical connection being free from metal.

In accordance with some embodiments, the electrical connection maycontain or may be made of polysilicon.

In accordance with some embodiments, the electrical connection maycontain or may be made of carbon.

In accordance with some embodiments, the electrical connection maycontain or may be made of a silicide.

In accordance with some embodiments, the electrical connection maycontain or may be made of a polycide.

In accordance with some embodiments, the method may further include:dicing the wafer along the kerf region after forming the electricalconnection.

In accordance with some embodiments, dicing the wafer along the kerfregion may include or may be achieved by sawing the wafer along the kerfregion.

In accordance with some embodiments, the electric or electronic devicemay include or may be a process control monitor (PCM) test device, andthe method may further include: carrying out a PCM test using the PCMtest device after forming the electrical connection and before dicingthe wafer.

A method of processing a wafer in accordance with various embodimentsmay include: providing a wafer, the wafer having a plurality ofintegrally-formed dies separated from each other by a kerf region formedbetween them, at least one of the plurality of dies having at least onepad containing or being made of a metal or a metal alloy, the waferfurther having at least one process control monitor (PCM) test deviceformed in the kerf region and connected to the at least one pad via atleast one electrical connection, the at least one electrical connectionbeing free from metal; and dicing the wafer along the kerf region.

In accordance with some embodiments, dicing the wafer along the kerfregion may include or may be achieved by sawing the wafer along the kerfregion.

In accordance with some embodiments, the at least one electricalconnection may include or may be made of polysilicon.

A wafer in accordance with various embodiments may include a pluralityof dies; a scribe line formed between at least two dies of the pluralityof dies and having at least one test device; at least one electricalconnection connecting the test device in the scribe line with at leastone pad of at least one die of the at least two dies, the at least oneelectrical connection being made of an electrically conductive materialother than a metal or metal alloy.

In accordance with some embodiments, the at least one pad may contain ormay be made of a metal or a metal alloy such as, for example, copper(Cu) or aluminum (Al), or an alloy containing Cu and/or Al.Alternatively or in addition, the at least one pad may contain or may bemade of other metals or metal alloys.

In accordance with some embodiments, the at least one test device mayinclude or may be a PCM (process control monitor) test device.

The wafer, or parts of the wafer, may further be configured inaccordance with one or more embodiments described herein.

A wafer in accordance with various embodiments may include: a pluralityof dies separated by a plurality of scribe lines; a plurality of PCMtest devices located in the scribe lines and connected to a plurality ofPCM pads of the plurality of dies by a plurality of electrical wiringscontaining polysilicon.

In accordance with some embodiments, the PCM pads may contain or may bemade of a metal or a metal alloy such as, for example, copper (Cu) oraluminum (Al), or an alloy containing Cu and/or Al. Alternatively or inaddition, the pads may contain or may be made of other metals or metalalloys.

In accordance with some embodiments, edges of the scribe lines locatednear or adjacent the dies may be free from metal.

The wafer, or one or more parts of the wafer, may further be configuredin accordance with one or more embodiments described herein.

A wafer in accordance with various embodiments may include: a kerfregion; an electric or electronic device in the kerf region; ametallization area outside the kerf region; an electrical connectionconnecting the electric or electronic device with the metallizationarea, the electrical connection being free from metal.

In accordance with some embodiments, the metallization area may includeor may be a pad, e.g. a PCM pad.

In accordance with some embodiments, the electric or electronic devicemay include or may be a test device, e.g. a PCM test device.

In the following, exemplary features and potential effects of exemplaryembodiments described herein are discussed.

In accordance with various embodiments, a new architecture for PCM/kerfstructures may be provided that may, for example, reduce or preventcrack formation during die singulation.

In accordance with various embodiments, one or more electric orelectronic devices, e.g. test devices such as PCM test devices, may beplaced in the kerf region (or scribe line) of a wafer while associatedpads (e.g. PCM pads) may be placed outside the kerf region (scribeline). In accordance with various embodiments, the devices may beconnected with the pads by means of one or more electrical connectionsthat are free from metal. In other words, the electrical connection orconnections may be made of a material or materials other than a metal ormetal alloy. For example, in accordance with some embodiments, theelectrical connection(s) may include or may be made of polysilicon orother suitable electrically conductive materials such as e.g. carbon, asilicide, a polycide, or doped semiconductor material (e.g. dopedsilicon) of the wafer.

In contrast to conventional architectures where PCM test devices andassociated pads are placed in the kerf region or scribe line(s) (seeFIG. 2), in the new architecture in accordance with various embodimentsthe PCM test devices may still be located in the kerf region or scribeline while the associated PCM pads may be located completely outside thekerf region or scribe line(s), and the wiring between the PCM testdevices and PCM pads may be realized by an electrically conductivematerial other than a metal or metal alloys, for example polysilicon.Illustratively, the wiring may cross the boundary between the kerfregion (scribe line) and one or more adjacent die regions.

This may, for example, have the effect that, on the one hand, the PCMdevices may still be removed in a dicing process (e.g. sawing process),which may prevent that fully functional single devices will be deliveredto the end customer (which might enable competitors to characterize thesingle devices), while, on the other hand, metal-induced crack formationduring dicing may be reduced or prevented since the PCM pads may belocated outside the kerf region or scribe line(s) so that the kerfregion or scribe line(s) may be substantially free from metal.

In accordance with various embodiments, PCM test devices may still belocated in the kerf region or dicing street(s) and removed later in thedicing process (e.g. sawing process), while the electrical connection(e.g. wiring) from the critical region (i.e. the dicing street(s) orregion(s) affected, e.g. destroyed, by the dicing) to one or moreassociated pads may be realized with electrically conductive materialother than a metal or metal alloy (e.g. polysilicon) and the pads maylie entirely outside the dicing street(s).

In accordance with various embodiments, the kerf region or dicingstreets of a wafer may be kept free or substantially free from metal byplacing comparatively large metallization areas such as e.g. PCM padsoutside the kerf region. Thus, potential crack formation atmetallization areas in the kerf region or dicing streets may be reducedor avoided. Furthermore, in accordance with various embodiments, PCMtest devices may still be placed in the kerf region or dicing streetsand may be removed or destroyed in a later dicing process. Thus, it maybe prevented that fully functional single devices will be delivered tothe end customer, as would be the case if the PCM test devices wereplaced outside the kerf region in the die regions. Furthermore, wafersin accordance with various embodiments may save wafer area compared e.g.to a wafer having one or more block PCMs (i.e. a wafer where one or moreof the die regions (e.g. one or more of the die regions 101 in FIG. 1)will be spared for forming a plurality of PCM test structures as a blockand will be discarded after the dicing of the wafer).

While the invention has been particularly shown and described withreference to specific embodiments, it should be understood by thoseskilled in the art that various changes in form and detail may be madetherein without departing from the spirit and scope of the invention asdefined by the appended claims. The scope of the invention is thusindicated by the appended claims and all changes which come within themeaning and range of equivalency of the claims are therefore intended tobe embraced.

What is claimed is:
 1. A die, comprising: a metallization area locatedproximate an edge of the die; an electrical connection connected to themetallization area and running from the metallization area to the edge,wherein the electrical connection is free from metal.
 2. The die ofclaim 1, wherein the electrical connection comprises an electricallyconductive trace disposed in the die, or on or above an upper surface ofthe die.
 3. The die of claim 2, wherein the electrical connectioncomprises polysilicon.
 4. The die of claim 1, wherein the electricalconnection comprises a doped region formed in the die.
 5. The die ofclaim 1, wherein the metallization area comprises a pad.
 6. A wafer,comprising: a die region comprising a metallization area; a kerf regioncomprising an electric or electronic device; an electrical connectionconnecting the electric or electronic device with the metallizationarea, wherein the electrical connection is free from metal.
 7. The waferof claim 6, wherein the electrical connection comprises an electricallyconductive trace disposed in the wafer, or on or above an upper surfaceof the wafer.
 8. The wafer of claim 7, wherein the electrical conductivetrace comprises polysilicon.
 9. The wafer of claim 6, wherein theelectrical connection comprises a doped region formed in the wafer. 10.The wafer of claim 6, wherein the metallization area comprises a pad.11. The wafer of claim 6, wherein the electric or electronic devicecomprises a test device.
 12. The wafer of claim 11, wherein the testdevice is a process control monitor (PCM) test device.
 13. A wafercomprising: a die region comprising a pad; a kerf region comprising atest device; an electrical connection connecting the test device in thekerf region with the pad in the die region, the electrical connectionbeing made of an electrically conductive material other than a metal ormetal alloy.
 14. The wafer of claim 13, wherein the test device is aprocess control monitor (PCM) test device.
 15. The wafer of claim 13,wherein the pad comprises a metal or a metal alloy.
 16. A wafer,comprising: a plurality of integrally-formed dies separated from eachother by a kerf region formed between them, at least one of theplurality of dies comprising at least one process control monitor (PCM)pad comprising a metal or a metal alloy; at least one PCM test devicelocated in the kerf region and electrically connected to the at leastone PCM pad via at least one electrical connection that is free frommetal.
 17. The wafer of claim 16, wherein the at least one electricalconnection comprises an electrically conductive trace comprisingpolysilicon and disposed in the wafer or on or above an upper surface ofthe wafer.
 18. The wafer of claim 16, wherein the at least oneelectrical connection comprises a doped region formed in the wafer. 19.A method of processing a wafer, the method comprising: providing a waferhaving a die region and a kerf region; forming an electric or electronicdevice in the kerf region; forming a metallization area in the dieregion; forming an electrical connection in or on the wafer connectingthe electric or electronic device with the metallization area, theelectrical connection being free from metal.
 20. The method of claim 19,wherein the electrical connection comprises polysilicon.
 21. The methodof claim 19, further comprising: dicing the wafer along the kerf regionafter forming the electrical connection.
 22. The method of claim 21,wherein the electric or electronic device comprises a process controlmonitor (PCM) test device and the metallization area comprises a PCMpad, the method further comprising: after forming the electricalconnection and before dicing the wafer, carrying out a PCM test usingthe PCM test device and the PCM pad.